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m48t37y M48T37V 3.3v-5v 256 kbit (32kb x8) timekeeper ? sram october 1998 1/20 integrated ultra-low power sram, real time clock, power-fail control circuit and battery frequency test output for real time clock year 2000 compliant automatic power-fail chip deselect and write protection watchdog timer write protect voltage (v pfd = power-fail deselect voltage): C m48t37y: 4.2v v pdf 4.5v C M48T37V: 2.7v v pfd 3.0v packaging includes a 44-lead soic and snaphat ? top (to be ordered separately) soic package provides direct connection for a snaphat top which contains the battery and crystal microprocessor power-on reset (valid even during battery back-up mode) programmable alarm output active in the battery backed-up description the m48t37y/37v timekeeper ? ram is a 32kb x8 non-volatile static ram and real time clock. the monolithic chip is available in a special package which provides a highly integrated battery backed- up memory and real time clock solution. ai02172 8 dq0-dq7 w v cc m48t37y M48T37V v ss g e wdi rst irq/ft 15 a0-a14 figure 1. logic diagram a0-a14 address input dq0-dq7 data input / output irq/ft interrupt / frequency test output (open drain) rst power fail reset output (open drain) wdi watchdog input e chip enable g output enable w write enable v cc supply voltage v ss ground table 1. signal names snaphat (sh) battery/crystal 44 1 soh44 (mh)
symbol parameter value unit t a ambient operating temperature 1 0 to 70 c 6 C40 to 85 t stg storage temperature (v cc off, oscillator off) snaphat C40 to 85 c soic C55 to 125 c t sld (2) lead solder temperature for 10 seconds 260 c v io input or output voltages m48t37y C0.3 to 7 v M48T37V C0.3 to 4.6 v v cc supply voltage m48t37y C0.3 to 7 v M48T37V C0.3 to 4.6 v i o output current 10 ma p d power dissipation 1 w notes: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal section of this specification is not implied. exposure to the absolute maximum rating conditions for extended periods of time m ay affect reliability. 2. soldering temperature not to exceed 260 c for 10 seconds (total thermal budget net to exceed 150 c for longer than 30 seconds). caution: negative undershoots below C0.3 volts are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. table 2. absolute maximum ratings (1) ai02174 22 44 43 v ss 1 a1 a7 a4 a3 a2 a6 a5 a13 nc a8 a9 nc a11 g e v cc m48t37y M48T37V 10 2 5 6 7 8 9 11 12 13 14 15 21 40 39 36 35 34 33 32 31 30 29 28 a12 a14 irq/ft nc 3 4 38 37 42 41 a0 dq0 dq7 dq5 dq1 dq2 dq3 dq4 dq6 16 17 18 19 20 27 26 25 24 23 wdi nc nc rst nc nc nc a10 nc nc w nc nc nc figure 2. soic pin connections warning: nc = not connected. the 44 lead 330mil soic package provides sock- ets with gold-plated contacts at both ends for direct connection to a separate snaphat housing con- taining the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. the snaphat housing is keyed to prevent reverse insertion. the soic and battery packages are shipped sepa- rately in plastic anti-static tubes or in tape &reel form. for the 44 lead soic, the battery/crystal package (i.e. snaphat) part number is "m4t28- br12sh1". as figure 3 shows, the static memory array and the quartz controlled clock oscillator of the m48t37y/37v are integrated on one silicon chip. the memory locations, to provide user accessible bytewide clock information are in the bytes with addresses 7ff1 and 7ff9h-7fffh (located in ta- ble 11). the clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour bcd format. corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. description (contd) 2/20 m48t37y, M48T37V
mode v cc e g w dq0-dq7 power deselect 4.5v to 5.5v (m48t37y) or 3.0v to 3.6v (M48T37V) v ih x x high z standby write v il xv il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (2) x x x high z cmos standby deselect v so x x x high z battery back-up mode notes : 1. x = v ih or v il ; v so = battery back-up switchover voltage. 2. see table 7 for details. table 3. operating modes (1) ai02175 lithium cell oscillator and clock chain v pfd rst v cc v ss 32,768 hz crystal voltage sense and switching circuitry 16 x 8 biport sram array 32,752 x 8 sram array a0-a14 dq0-dq7 e w g power irq/ft wdi battery low figure 3. block diagram 3/20 m48t37y, M48T37V
ai02325 c l = 100pf c l includes jig capacitance 645 w device under test 1.75v figure 4. ac testing load circuit input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v note that output hi-z is defined as the point where data is no longer driven. table 4. ac measurement conditions symbol parameter test condition min max unit c in input capacitance v in = 0v 10 pf c io (3) input / output capacitance v out = 0v 10 pf notes: 1. effective capacitance measured with power supply at 5v. 2. sampled only, not 100% tested. 3. outputs deselected table 5. capacitance (1, 2) (t a = 25 c, f = 1 mhz ) symb parameter test condition m48t37y M48T37V unit v cc = 4.5v to 5.5v v cc = 3.0v to 3.6v min max min max i li (1) input leakage current 0v v in v cc 1 1 m a i lo (1) output leakage current 0v v out v cc 5 5 m a i cc supply current outputs open 50 33 ma i cc1 supply current (standby) ttl e = v ih 32ma i cc2 supply current (standby) cmos e = v cc C 0.2v 3 2 ma v il (2) input low voltage C0.3 0.8 C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage (standard) i ol = 2.1ma 0.4 0.4 v output low voltage (open drain) i ol = 10ma 0.4 0.4 v v oh (2) output high voltage i oh = C1ma 2.4 2.4 v notes: 1. outputs deselected. 2. negative spikes of C1v allowed for up to 10ns once per cycle. table 6. dc characteristics (t a = 0 to 70 c) 4/20 m48t37y, M48T37V
symbol parameter min typ max unit v pfd power-fail deselect voltage (m48t37y, 5v) 4.2 4.4 4.5 v power-fail deselect voltage (M48T37V, 3.3v) 2.7 2.9 3.0 v v so battery back-up switchover voltage (5v) v bat v battery back-up switchover voltage (3.3v) v pfd C100mv v t dr expected data retention time (25 c) grade 1 7 years grade 6 10 (2) notes: 1. all voltages referenced to v ss . 2. using larger m4t32-br12sh6 snaphat top (recommended for industrial temperature - grade 6 device). table 7. power down/up trip points dc characteristics (1) (t a = 0 to 70 c) symbol parameter min max unit t f (1) v pfd (max) to v pfd (min) v cc fall time 300 m s t fb (2) v pfd (min) to v so v cc fall time 10 m s t r v pfd (min) to v pfd (max) v cc rise time 10 m s t rb v so to v pfd (min) v cc rise time 1 m s t rec (3) v pfd (max) to rst high 40 200 ms notes :1.v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 m s after v cc passes v pfd (min). 2. v pfd (min) to v so fall time of less than t fb may cause corruption of ram data. 3. t rec (min) = 20ms for industrial temperature grade 6 device. table 8. power down/up mode ac characteristics (t a = 0 to 70 c) symbol parameter m48t37y M48T37V unit v cc = 4.5v to 5.5v v cc = 3.0v to 3.6v -70 -100 min max min max t avav read cycle time 70 100 ns t avqv (1) address valid to output valid 70 100 ns t elqv (1) chip enable low to output valid 70 100 ns t glqv (1) output enable low to output valid 35 50 ns t elqx (2) chip enable low to output transition 5 10 ns t glqx (2) output enable low to output transition 5 5 ns t ehqz (2) chip enable high to output hi-z 25 50 ns t ghqz (2) output enable high to output hi-z 25 40 ns t axqx (1) address transition to output transition 10 10 ns notes: 1. c l = 100pf (see figure 4). 2. c l = 5pf (see figure 4). table 9. read mode ac characteristics (t a = 0 to 70 c) 5/20 m48t37y, M48T37V
ai02177 v cc inputs rst outputs don't care high-z tf tfb tr trec trb tdr valid valid v pfd (max) v pfd (min) v so valid valid figure 5. power down/up mode ac waveforms ai00925 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a14 e g dq0-dq7 valid figure 6. read mode ac waveforms note: write enable ( w) = high. 6/20 m48t37y, M48T37V
ai00926 tavav twhax tdvwh data input a0-a14 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx figure 7. write enable controlled, write ac waveforms ai00927 tavav tehax tdveh a0-a14 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input figure 8. chip enable controlled, write ac waveforms 7/20 m48t37y, M48T37V
symbol parameter m48t37y M48T37V unit v cc = 4.5v to 5.5v v cc = 3.0v to 3.6v -70 -100 min max min max t avav write cycle time 70 100 ns t avw l address valid to write enable low 0 0 ns t avel address valid to chip enable low 0 0 ns t wlwh write enable pulse width 50 80 ns t eleh chip enable low to chip enable high 55 80 ns t whax write enable high to address transition 0 10 ns t ehax chip enable high to address transition 0 10 ns t dvwh input valid to write enable high 30 50 ns t dveh input valid to chip enable high 30 50 ns t whdx write enable high to input transition 5 5 ns t ehdx chip enable high to input transition 5 5 ns t wlqz (1, 2) write enable low to output hi-z 25 50 ns t avw h address valid to write enable high 60 80 ns t av e1h address valid to chip enable high 60 80 ns t whqx (1, 2) write enable high to output transition 5 10 ns notes: 1. c l = 5pf (see figure 4). 2. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. table 10. write mode ac characteristics (t a = 0 to 70 c) byte 7ff8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. byte 7ff7h contains the watchdog timer setting. the watchdog timer redirects an out-of-control mi- croprocessor and provides a reset or interrupt to it. byte 7ff2h-7ff5h are reserved for clock alarm programming. these bytes can be used to set the alarm. this will generate an active low signal on the irq/ft pin when the alarm bytes match the date, hours, minutes and seconds of the clock. the eight clock bytes are not the actual clock counters them- selves; they are memory locations consisting of biport ? read/write memory cells. the m48t37y/37v includes a clock control circuit which updates the clock bytes with current information once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the m48t37y/37v also has its own power-fail detect circuit. the control circuitry constantly moni- tors the single v cc supply for an out of tolerance condition. when vcc is out of tolerance, the circuit writes protects the sram, providing a high degree of data security in the midst of unpredictable sys- tem operation brought on by low v cc . as v cc falls below the battery back-up switchover voltage (v so ), the control circuitry connects the battery which maintains data and clock operation until valid power returns. read mode the m48t37y/37v is in the read mode whenever write enable ( w) is high and chip enable ( e) is low. the unique address specified by the 15 address inputs defines which one of the 32,752 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and output enable ( g) access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). description (contd) 8/20 m48t37y, M48T37V
the state of the eight three-state data i/o signals is controlled by e and g. if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain active, output data will remain valid for output data hold time (t axqx ) but will be indeterminate until the next address access. write mode the m48t37y/37v is in the write mode whenever w and e are low. the start of a write is referenced from the latter occurring falling edge of w or e. a write is terminated by the earlier rising edge of w or e. the addresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g a low on w will disable the outputs t wlqz after w falls. data retention mode with valid v cc applied, the m48t37y/37v operates as a conventional bytewide tm static ram. should the supply voltage decay, the ram will automatically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as "dont care". address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 7fffh 10 years year year 00-99 7ffeh 0 0 0 10 m month month 01-12 7ffdh 0 0 10 date date date 01-31 7ffch 0 ft 0 0 0 day day 01-07 7ffbh 0 0 10 hours hours hour 00-23 7ffah 0 10 minutes minutes minutes 00-59 7ff9h st 10 seconds seconds seconds 00-59 7ff8h w r s calibration control 7ff7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 7ff6h afe 0 abe 0 0 0 0 0 interrupts 7ff5h rpt4 0 al. 10 date alarm date alarm date 01-31 7ff4h rpt3 0 al. 10 hours alarm hours alarm hours 00-23 7ff3h rpt2 alarm 10 minutes alarm minutes alarm minutes 00-59 7ff2h rpt1 alarm 10 seconds alarm seconds alarm seconds 00-59 7ff1h 1000 years 100 years century 00-99 7ff0h wdf af z bl z z z z flags table 11. register map keys: s = sign bit ft = frequency test bit r = read bit w = write bit st = stop bit 0 = must be set to 0 z = 0 and are read only wds = watchdog steering bit af = alarm flag bl = battery low flag wds = watchdog steering bit bmb0-bmb4 = watchdog multiplier bits rb0-rb1 = watchdog resolution bits afe = alarm flag enable abe = alarm in battery back-up mode enable rpt1-rpt4 = alarm repeat mode bits wdf = watchdog flag read mode (contd) 9/20 m48t37y, M48T37V
note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the rams content. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the vcc fall time is not less than t f . the m48t37y/37v may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . there- fore, decoupling of the power supply lines is rec- ommended. when v cc drops below v so , the control circuit switches power to the internal battery which preserves data and powers the clock. the internal button cell will maintain data in the m48t37y/37v for an accumulated period of at least 7 years at room temperature when v cc is less than v so . as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . normal ram operation can resume t rec after v cc reaches v pfd (max). for more information on battery storage life refer to the application note an1012. power-on reset the m48t37y/37v continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for 40ms to 200ms after v cc passes v pfd . rst is valid for all v cc conditions. the rst pin is an open drain output and an appropriate resistor should be chosen to control rise time. programmable interrupts the m48t37y/37v provides two programmable interrupts; an alarm and a watchdog. when an interrupt condition occurs, the m48t37y/37v sets the appropriate flag bit in the flag register 7ff0h. the interrupt enable bits in (afe and abe) in 7ff6h and the watchdog steering (wds) bit in 7ff7h allow the interrupt to activate the irq/ft pin. the interrupt flags and the irq/ft output are cleared by a read to the flags register. an interrupt condition reset will not occur unless the addresses are stable at the flag location for at least 15ns while the device is in the read mode as shown in figure 11. the irq/ft pin is an open drain output and re- quires a pull-up resistor (10k w recommended). the pin remains in the high impedance state unless an interrupt occurs or the frequency test mode is enabled. clock operations reading the clock updates to the timekeeper registers should be halted before clock data is read to prevent reading data in transition. because the biport time- keeper cells in the ram array are only data registers, and not the actual clock counters, updat- ing the registers can be halted without disturbing the clock itself. updating is halted when a 1 is written to the read bit, d6 in the control register 7ff8h. as long as a 1 remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating will resume within a second after the bit is reset to a 0. ai00594b normal positive calibration negative calibration figure 9. clock calibration 10/20 m48t37y, M48T37V
setting the clock bit d7 of the control register 7ff8h is the write bit. setting the write bit to a 1, like the read bit, halts updates to the timekeeper registers. the user can then load them with the correct day, date, and time data in 24 hour bcd format (see table 11). resetting the write bit to a 0 then transfers the values of all time registers 7ff9h-7fffh to the actual timekeeper counters and allows normal operation to resume. after the write bit is reset, the next clock update will occur in approximately one second. note: upon power-up following a power failure, both the write bit and the read bit will be reset to 0. stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is the msb of the seconds register. setting it to a 1 stops the oscillator. the m48t37y/37v is shipped from st with the stop bit set to a 1. when reset to a 0, the m48t37y/37v oscillator starts within one second. note : it is not necessary to set the write bit when setting or resetting the frequency test bit (ft) or the stop bit (st). calibrating the clock the m48t37y/37v is driven by a quartz controlled oscillator with a nominal frequency of 32,768 hz. the devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m48t37y/37v improves to better than + 4 / C2 ppm at 25c. the oscillation rate of any crystal changes with temperature (see figure 10). most clock chips com- pensate for crystal frequency and temperature shift error with cumbersome trim capacitors. the m48t37y/37v design, however, employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in figure 9. the number of times pulses are blanked (sub- tracted, negative calibration) or split (added, posi- tive calibration) depends upon the value loaded into the five bit calibration byte found in the control register. adding counts speeds the clock up, sub- tracting counts slows the clock down. the calibration byte occupies the five lower order bits (d4-d0) in the control register 7ff8h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; 1 indicates positive calibration, 0 indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary 1 is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 (64 minutes x 60 seconds/min- ute x 32,768 cycles/second) actual oscillator cy- cles, that is +4.068 or C2.034 ppm of adjustment per calibration step in the calibration register. as- suming that the oscillator is in fact running at ex- actly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or C5.35 seconds per month which corresponds to a total range of +5.5 or C2.75 minutes per month. two methods are available for ascertaining how much calibration a given m48t37y/37v may re- quire. the first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like www broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. all the designer has to do is provide a simple utility that accesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the irq/ft pin. the pin will toggle at 512hz when the stop bit (st, d7 of 7ff9h) is 0, the frequency test bit (ft, d6 of 7ffch) is 1, the alarm flag enable bit (afe, d7 of 7ff6h) is 0, and the watchdog steering bit (wds, d7 of 7ff7h) is 1 or the watchdog register is reset (7ff7h=0). any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.01024 hz would indicate a +20 ppm oscillator frequency error, requiring a C10(wr001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. the irq/ft pin is an open drain output which requires a pull-up resistor for proper operation. a 500-10k w resistor is recommended in order to control the rise time. the ft bit is cleared on power-up. 11/20 m48t37y, M48T37V
setting alarm clock registers 7ff5h-7ff2h contain the alarm settings. the alarm can be configured to go off at a predeter- mined time on a specific day of the month or repeat every day, hour, minute, or second. it can also be programmed to go off while the m48t37y/37v is in the battery back-up mode of operation to serve as a system wake-up call. rpt1-rpt4 put the alarm in the repeat mode of operation. table 12 shows the possible configura- tions. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt1-rpt4, af is set. if afe is also set, the alarm condition activates the irq/ft pin. the alarm flag and the irq/ft output are cleared by a read to the flags register as shown in figure 11. the irq/ft pin can also be activated in the battery back-up mode. the irq/ft will go low if an alarm occurs and both alarm in battery back-up mode enable (abe) and afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot-up to determine if an alarm was generated while the m48t37y/37v was in the deselect mode during power-up. figure 12 illustrates the back-up mode alarm timing. ai00999 C160 0 10203040506070 frequency (ppm) temperature c 80 C10 C20 C30 C40 C100 C120 C140 C40 C60 C80 20 0 C20 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c figure 10. crystal accuracy across temperature 12/20 m48t37y, M48T37V
watchdog timer the watchdog timer can be used to detect an out-of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the eight bit watchdog register, address 7ff7h. the five bits (bmb4-bmb0) store a binary multiplier and the two lower order bits (rb1-rb0) select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. the amount of time-out is then deter- mined to be the multiplication of the five bit multi- plier value with the resolution. (for example: writing 00001110 in the watchdog register = 3x1 or 3 seconds). if the processor does not reset the timer within the specified period, the m48t37y/37v sets the watchdog flag (wdf) and generates a watchdog interrupt or a microprocessor reset. the most significant bit of the watchdog register is the watchdog steering bit. when set to a 0, the watchdog will activate the irq/ft pin when timed- out. when wds is set to a 1, the watchdog will output a negative pulse on the rst pin for a duration of 40ms to 200ms. the watchdog register and the ft bit will reset to a 0 at the end of a watchdog time-out when the wds bit is set to a 1. the watchdog timer resets when the microproces- sor performs a re-write of the watchdog register or an edge transition, (low to high / high to low) on the wdi pin occurs. the time-out period then starts over. the watchdog timer is disabled by writing a value of 00000000 to the eight bits in the watchdog register. should the watchdog timer time out, a value of 00h needs to be written to the watchdog register inorder to clear the irq/ft pin. the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set to output to the irq/ft pin and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. the wdi pin contains a pull-down resistor which is greater than 100k w , and therefore can be left unconnected if not used. rpt4 rpt3 rpt2 rpt1 alarm activated 1 1 1 1 once per second 1 1 1 0 once per minute 1 1 0 0 once per hour 1 0 0 0 once per day table 12. alarm repeat mode ai01677b a0-a14 active flag bit address 7ff0h irq/ft 15ns min figure 11. interrupt reset waveforms 13/20 m48t37y, M48T37V
battery low flag the m48t37y/37v automatically performs peri- odic battery voltage monitoring upon power-up and at factory-programmed time intervals of 24 hours. the battery low flag (bl), bit d4 of flags register 7ff0h, will be asserted high if the internal or snaphat battery is found to be less than approxi- mately 2.5v. the bl flag will remain active until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5v (approx.), which may be insufficient to maintain data integrity. data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. however, data has not been compromised due to the fact that a nominal vcc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, it is recommended that the battery be replaced. note: battery monitoring is a useful technique only when performed periodically. the m48t37y/37v only monitors the battery when a nominal vcc is applied to the device. thus applications which re- quire extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. power-on defaults upon application of power to the device, the follow- ing register bits are set to a 0 state: wds; bmb0- bmb4; rb0-rb1; afe; abe; w; r; ft. ai01678b v cc irq/ft high-z v pfd (max) v pfd (min) afe bit in interrupt register af bit in flags register high-z v so figure 12. back-up mode alarm waveforms 14/20 m48t37y, M48T37V
power supply decoupling and under- shoot protection i cc transients, including those produced by output switching, can produce voltage fluctuations, result- ing in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy, which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic bypass capaci- tor value of 0.1 m f (as shown in figure 13) is recommended in order to provide the needed filter- ing. in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to connect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. ai02169 v cc 0.1 m f device v cc v ss figure 13. supply voltage protection 15/20 m48t37y, M48T37V
ordering information scheme supply voltage and write protect voltage 37y v cc = 4.5v to 5.5v v pfd = 4.2v to 4.5v 37v v cc = 3.0v to 3.6v v pfd = 2.7v to 3.0v speed -70 70ns -10 100ns package mh (1) soh44 temp. range 1 0 to 70 c 6 C40 to 85 c shipping method for soic blank tubes tr tape & reel example: m48t37y -70 mh 1 tr note: 1. the soic package (soh44) requires the battery/crystal package (snaphat) which is ordered separately under the part number "m4txx-br12sh1" in plastic tube or "m4txx-br12sh1tr" in tape & reel form. caution: do not place the snaphat battery/crystal package "m4txx-br12sh1" in conductive foam since this w ill drain the lithium button-cell battery. for a list of available options (package, etc...) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. 16/20 m48t37y, M48T37V
soh e n d c l a1 a 1 h a cp be a2 eb symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.46 0.014 0.018 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e0.81C C0.032C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n44 44 cp 0.10 0.004 drawing is not to scale. soh44 - 44 lead plastic small outline, battery snaphat 17/20 m48t37y, M48T37V
sh a1 a d e ea eb a2 b l a3 symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 drawing is not to scale. m4t28-br12sh - snaphat housing for 28 lead plastic small outline 18/20 m48t37y, M48T37V
sh a1 a d e ea eb a2 b l a3 symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 m4t32-br12sh - snaphat housing for 32 lead plastic small outline drawing is not to scale. 19/20 m48t37y, M48T37V
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics product s are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved ? timekeeper and snaphat are registered trademarks of stmicroelectronics tm biport is a trademark of stmicroelectronics stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 20/20 m48t37y, M48T37V

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